Job Details:Job Description: Develops, maintains, and ensures quality assurance of process design kit (PDK) collateral, including PDK Full chip collateral Libraries for Intel design teams to enable new processes and methodologies to be followed across Intel's product lines. Develops automation of QA flow methodologies for specific technology nodes to scale up QA coverage. Documents and monitors QA results. May include developing test patterns to qualify the physical design rules for correct implementations. Performs validation for PDK library covering collaterals, partition cells, 3DIC packaging, and back end physical design checks. Leads root cause analysis for issues related to designing to a specific process technology and continuously drives initiatives to enhance design methodologies. Creates and maintains technology files , test suites design rule checks, and/or layout versus schematic runsets for silicon designers to understand the design process. Resolves issues and bugs found within the PDK collateral. May also deliver design flows, guidelines, and tutorials through sample design databases, test chips, and libraries. Collaborates with silicon design, process engineering, and high volume manufacturing teams to identify new process technologies and ensure new solutions are high quality and ensure ease of use for both internal and external design communities. Works with EDA vendors on tool improvements to enhance performance and add functionality.
Qualifications:Candidate should have hands on experience along with technical management on PDK and full chip finishing cells, bumps usage with APR tools usage across EDA breadth - Cadence Innovus, Synopsis Fusion compiler, physical verification tools - ICV, Caliber and Pegasus, runset errors analysis and dispositioning. Automation knowledge in TCL, Skill and Python is required. Should work with multiple stake holders in arriving at specification for bumps , develops and performs validation. Working knowledge of various interconnects (such as bumps, pads) is a plus. Report issues found with PDK validation, work with stake holders and vendors in issues resolution and verification on fixes. Good written and verbal communication skills required. B.Tech/M.Tech with 12+ years of experienceJob Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Business group:As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
