Staff Engineer - AMS Verification

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY22 and approximately 25,000 people globally working alongside 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible.

Staff Mixed Signal Design Verification Engineer

Digital Business Unit (DBU)

Analog Devices is seeking Mixed Signal Design Verification Engineer for a Staff level role, who will be responsible for design verification of highly integrated solutions and products in a multifunctional team. You will be working on driving real revenue growth on the next generation of Intelligence at the Edge products across multiple products and business units.

About the Role

Key member of design verification team, which has both mixed-signal and digital design verification engineers. The candidate will be responsible for formulating verification strategies and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI.   The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible.

Requirements

• B.Tech/M.Tech with 8+ years of industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (AMS and DMS DV).
• Good understanding of analog design concepts and mixed signal design architectures. Exposure to products that integrate a wide variety of Analog/Mixed-Signal/RF building blocks such as Power Management, ADCs, DACs, PLL, bandgap references, oscillators, SerDes, RF Transceiver etc. and related digital control and signal processing.
• Demonstrated experience of verification plan, verification environment development and verification/debug of complex mixed signal products at block & chip-top levels.
• Experience of co-simulations with analog model/transistor level and digital RTL/Gate+SDFs, experience of circuit simulations with Spice/Fast Spice simulators.
• Proven experience in closing the verification of analog designs using industry standard metrics is a must.
• Exceptional interpersonal and communication skills, collaborate and influence innovative design development/verification methodologies to wider team spread across the globe.
• Proficiency in the technical management of AMS team execution is a must.
• Quick to adopt new technologies with good problem-solving skills.
• Self-motivated and enthusiastic.

Responsibilities

• Come up with verification strategy for a product after going through product requirements and design specifications.
• Create models for analog/mixed-signal blocks for chip-top verification, tradeoff accuracy vs. speed. Validate models against actual design (self-checking tests).
• Create verification plans, build verification environment, develop self-checking testcases. Bring up chip top mixed-signal verification environments (AMS and DMS DV environments).
• Deploy industry standard SV/UVM based metric driven verification approach.
• Collaborate and work closely with team members from various disciplines (system architects, digital design, analog design, digital DV etc.) for first pass silicon.
• Support test and characterization teams in post-silicon validation.
• Collaborate with CAD team to deploy next generation innovative design verification methodologies to reduce overall TTM, mentor junior DV engineers in the team.
• Expected to be the overall AMS DV lead of a project.
• Mentor fresh graduates and junior engineers.

Skill Set [Experience of following is desired, not all but most of them]

Modelling of analog blocks

SV-RNM

Verilog-AMS

Schematic based structural models (macro models)

Familiarity with Analog/Mixed-Signal/RF design architectures and debug experience with schematic capture tools such as Cadence Virtuoso and waveform viewers such as Cadence Simvision. Chip-top co-simulation with tools such as Cadence ADE/Cadence AMSD with Spectre as the analog solver and Xcelium as the digital solver. Experience and debug with digital simulators such as Cadence Xcelium/Synopsys VCS. Experience with Spice/Fast Spice simulators such as Spectre Ultrasim/APS/XPS. Experience with SV/UVM (agent creation, env building, score-boarding, RAL etc.). Experience with simulation emulation accelerators. Tracking of verification metrics and regression management, Metric Driven Verification (MDV) framework using tools such as Cadence vManager. Experience with languages/tools/software relating to product development is an added advantage.

C, C++, AMS

Automation with scripting languages: Python/Perl/Shell etc.

Embedded programming for on-chip micros or separate MCU’s

Matlab/Simulink for system level simulations and modeling

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.