General Summary:
Responsiblities:
Full chip synthesis using Synopsys Design Compiler and Design Compiler-Topographical
Constraints development, Static Timing Analysis & timing closure
Work closely with design team to come up with preplacement requirements & timing constraints
Work closely with physical design team for floorplan, placement & timing reviews
Work closely with cross-functional teams to review standard cell profile, timing models & memory models
Skills/Experience:
4 to 8 years of experience in digital design
Good understanding of SoC ASIC design flow
Hands on experience in full chip synthesis and static timing analysis
Proficiency with Synopsys DC & PT tools and Verilog/VHDL is a must
Good knowledge of IO interfaces like DDR, SDCC, HSIC, SPI is a must
Knowledge of ARM Processors, Ethernet MAC, PCIE and Bus protocols like AHB, AXI etc desirable
Experience in Perl, TCL and shell scripting is desirable
Excellent interpersonal & analytical skills with ability to work independently
Minimum Qualifications:
Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email toaccommodationsupport
Although this role has some expected minor physical activity, this should not deter otherwise qualified applicants from applying. If you are an individual with a physical or mental disability and need an accommodation during the application/hiring process, please call Qualcomm’s toll-free number found herefor assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities as part of our ongoing efforts to create an accessible workplace.
Qualcomm is an equal opportunity employer and supports workforce diversity.
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